 rtd_maskl(0xb8008908, 0xfffffffe, 0x00000000);       //disable on the fly calibration function
 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC
 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000000);       //tap 0
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_inl(0xb8029038) --> 0x93e0c957;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000022;       //------------------> error count
 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC
 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000041);       //tap 1
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_inl(0xb8029038) --> 0x81966b67;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000022;       //------------------> error count
 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC
 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000082);       //tap 2
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_inl(0xb8029038) --> 0xfb5ce23e;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000021;       //------------------> error count
 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC
 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000093);       //tap 3
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay
 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xdeb2674f;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count
 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC
 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000104);       //tap 4
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay
 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xdcbb7d1f;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001b;       //------------------> error count
 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC
 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000145);       //tap 5
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay
 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xbdf5f70f;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count
 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC
 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000186);       //tap 6
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay
 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x449002fd;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count
 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC
 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x000001c7);       //tap 7
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay
 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x3402f92a;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count
 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC
 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000208);       //tap 8
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay
 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xa3f9aa58;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count
 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC
 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000249);       //tap 9
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay
 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x8832cdeb;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count
 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC
 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x0000028a);       //tap 10
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay
 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x11fb6da7;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count
 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC
 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x000002cb);       //tap 11
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xbfdaef2a;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x0000030c);       //tap 12
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x236b67e1;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001b;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x0000034d);       //tap 13
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xc5f8163a;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x0000038e);       //tap 14
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000100);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_inl(0xb8029038) --> 0x38f71cad;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000022;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x000003cf);       //tap 15
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x42c7ed70;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000410);       //tap 16
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000451);       //tap 17
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000492);       //tap 18
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x000004d3);       //tap 19
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000514);       //tap 20
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000555);       //tap 21
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000596);       //tap 22
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x000005d7);       //tap 23
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000618);       //tap 24
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000659);       //tap 25
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x0000069a);       //tap 26
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x000006db);       //tap 27
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x0000071c);       //tap 28
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x0000075d);       //tap 29
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x0000079e);       //tap 30
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x70e2ae8d;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000010;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x000007df);       //tap 31
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x8b6b02d3;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000017;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000820);       //tap 32
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x26136138;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000861);       //tap 33
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x0914b50c;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x000008a2);       //tap 34
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x5ce971d4;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x000008e3);       //tap 35
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x09980eca;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000924);       //tap 36
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xb5a00970;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000965);       //tap 37
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xf26a85f0;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001b;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x000009a6);       //tap 38
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x9eb05c5d;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x000009e7);       //tap 39
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xada9e057;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000a28);       //tap 40
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xba6e801b;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000a69);       //tap 41
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xc90a0c25;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000aaa);       //tap 42
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x1216ca3f;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000aeb);       //tap 43
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x1bf28070;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000b2c);       //tap 44
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xd3779ef6;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000b6d);       //tap 45
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe91737b7;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001b;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000bae);       //tap 46
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x55977d8a;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000bef);       //tap 47
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xf091f0a4;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000c30);       //tap 48
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xf0be4f9b;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000c71);       //tap 49
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xc2108462;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000cb2);       //tap 50
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xa7c6fdb6;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000cf3);       //tap 51
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xcc0456d4;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000d34);       //tap 52
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe20b4f75;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000d75);       //tap 53
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xfda4dba9;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000db6);       //tap 54
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x1dd4e624;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000df7);       //tap 55
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xa72536a8;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001b;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000e38);       //tap 56
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xc388bac5;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000e79);       //tap 57
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x9c409ddb;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000eba);       //tap 58
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xc77f37ef;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000efb);       //tap 59
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x4c444861;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000f3c);       //tap 60
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x6c25218c;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000f7d);       //tap 61
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x21afa65a;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001a;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000fbe);       //tap 62
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x42b89053;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001b;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x00000fff);       //tap 63
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0x61e26cc3;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x0000001b;       //------------------> error count

 rtd_outl(0xb8029034, 0x000a1800);       //disable MEM crc
 rtd_outl(0xb80290e0, 0x00000000);       //enable auto compare CRC

 rtd_outl(0xb802732C, 0x00000040);       //disp disable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 rtd_outl(0xb8008838, 0x00000000); 
 rtd_outl(0xb8008880, 0x000009a6);       //tap 38s
 rtd_outl(0xb8008838, 0x03000000); 
 rtd_outl(0xb802732C, 0x00000041);       //disp enable
 rtd_outl(0xb8027334, 0x00000001);       //double buffer reg enable
 ScalerTimer_DelayXms(0x00000200);       //short delay

 rtd_outl(0xb8029034, 0x000a1803);       //enable MEM crc
 ScalerTimer_DelayXms(0x00000200);       //short delay
 rtd_outl(0xb80290e0, 0x00000002);       //enable auto compare CRC
 ScalerTimer_DelayXms(0x00000200);       //short delay

 ScalerTimer_DelayXms(0x00000100);       //short delay
 rtd_inl(0xb8029038) --> 0xe9df1195;       //------------------> CRC
 rtd_inl(0xb80290f0) --> 0x00000000;       //------------------> error count
