<?xml version="1.0" encoding="iso8859-1" standalone="yes"?>
<RegisterBase CHIP = "Picasso">
   <Group Name = "I domain">
     <RegisterGroup Name = "LVDS_RX_PHY">
         <RegisterSet Name = "LVDS RX PHY">
             <Register Name = "lvds_rx_phy_ctl0" Address = "2040">
                 <RegisterBit Name ="adjr_z0" StartBit = "11" BitCount = "3" RW = "2" default = "8">
                     <![CDATA[ 
                      Z0 50Ohm calibration  default reg
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="adjr_os" StartBit = "7" BitCount = "3" RW = "2" default = "7">
                     <![CDATA[ 
                      input RXAMP offset calibration default reg
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="auto_k_os" StartBit = "3" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      input RXAMP offset calibration enable reg
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="even_en" StartBit = "2" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      E lane enable
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="odd_en" StartBit = "1" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      O lane enable
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="auto_k_z0" StartBit = "0" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Z0 50 Ohm auto calibration enable reg
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "lvds_rx_phy_ctl1" Address = "2044">
                 <RegisterBit Name ="reg_blskwa" StartBit = "23" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      ODD lane skew adjust reg:
                       step:30ps;total skew delay:450ps
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_blskwb" StartBit = "19" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      ODD lane skew adjust reg:
                       step:30ps;total skew delay:450ps
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_blskwc" StartBit = "15" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      ODD lane skew adjust reg:
                       step:30ps;total skew delay:450ps
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_blskwck" StartBit = "11" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      ODD lane skew adjust reg:
                       step:30ps;total skew delay:450ps
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_blskwd" StartBit = "7" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      ODD lane skew adjust reg:
                       step:30ps;total skew delay:450ps
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_blskwe" StartBit = "3" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      ODD lane skew adjust reg:
                       step:30ps;total skew delay:450ps
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "lvds_rx_phy_ctl2" Address = "2048">
                 <RegisterBit Name ="reg_alskwa" StartBit = "23" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      EVEN lane skew adjust reg:
                       step:30ps;total skew delay:450ps
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_alskwb" StartBit = "19" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      EVEN lane skew adjust reg:
                       step:30ps;total skew delay:450ps
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_alskwc" StartBit = "15" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      EVEN lane skew adjust reg:
                       step:30ps;total skew delay:450ps
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_alskwck" StartBit = "11" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      EVEN lane skew adjust reg:
                       step:30ps;total skew delay:450ps
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_alskwd" StartBit = "7" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      EVEN lane skew adjust reg:
                       step:30ps;total skew delay:450ps
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_alskwe" StartBit = "3" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      EVEN lane skew adjust reg:
                       step:30ps;total skew delay:450ps
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "lvds_rx_phy_ctl3" Address = "204C">
                 <RegisterBit Name ="reg_rxpll_cp" StartBit = "22" BitCount = "1" RW = "2" default = "3">
                     <![CDATA[ 
                      LVDSRX PLL loop Filter C1:
                       00:55pf;01:60pf;10:65pf;11:70pf
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_rxpll_cs" StartBit = "20" BitCount = "1" RW = "2" default = "1">
                     <![CDATA[ 
                      LVDSRX PLL loop Filter C2:
                       00:1.5pf;01:2pf;10:2.5pf;11:3pf
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_rxpll_rs" StartBit = "18" BitCount = "2" RW = "2" default = "2">
                     <![CDATA[ 
                      LVDSRX PLL loop filter Rs:
                       000:2K;001:4K;010:6K;011:8K;100:12K;101:16K;110:24K;111:32K
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_rxpll_ip" StartBit = "15" BitCount = "3" RW = "2" default = "7">
                     <![CDATA[ 
                      LVDSRX PLL charge pump current:
                       0000:0uA;0010:5uA;0100:10uA;1000:20uA
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="seqcl" StartBit = "11" BitCount = "1" RW = "2" default = "2">
                     <![CDATA[ 
                      LVDSRX AMP equalizer CS selection:
                       00:0.8pf;01:1.04pf;10:1.28pf;11:1.52pf
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="seqrl" StartBit = "9" BitCount = "1" RW = "2" default = "2">
                     <![CDATA[ 
                      LVDSRX AMP equalizer RS selection:
                       00:1.2K;01:0.92K;10:0.8K;11:0.73K
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="z0_en" StartBit = "7" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      LVDSRX Z0 50OHM enable reg:
                       0: open;1: 50ohm
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_bg_rs" StartBit = "6" BitCount = "1" RW = "2" default = "2">
                     <![CDATA[ 
                      LVDSRX bias current adjust reg:
                       00:60uA;01:55uA;10:50uA;11:46uA
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_selvcod2" StartBit = "4" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      LVDSRX PLL VCO work range selection:
                       1'b0:Fvco=Fref*7;1'b1:Fvco=Fref*14
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="reg_tstmux" StartBit = "3" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      LVDSRX test mode output selection:
                       0000-0101:<EVEV lane RXAMP offset calibration result(osok,os_reg<3:0>)>;0110:<EVEN lane rxamp output signal<4:0>>;0111:<even lane rxamp ck output,Z0 calibration result<3:0>>;1xxx:LVDSRX  <Even lane PLL CLK2X,Odd lane PLL CLK2X,Even lane PLL feedback clk,Odd lane PLL feedback clk,ti0>
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "lvds_rx_phy_pll_ctl0" Address = "2050">
                 <RegisterBit Name ="mcode" StartBit = "29" BitCount = "9" RW = "2" default = "1e">
                     <![CDATA[ 
                      27Mhz freerun PLL loop divider register:
                       N+2 divider
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ncode" StartBit = "19" BitCount = "7" RW = "2" default = "2">
                     <![CDATA[ 
                      27Mhz freerun predivider register:
                       N+2 divider
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ocode" StartBit = "5" BitCount = "1" RW = "2" default = "2">
                     <![CDATA[ 
                      27Mhz freerun PLL post divider register:
                       00:DIV1;01:DIV2;10:DIV4;11:DIV8
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="freerun_en" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      27Mhz freerun enable register:
                       1'b0:disable 27M freerun;1'b1:enable 27m freerun
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "lvds_rx_phy_pll_ctl1" Address = "2054">
                 <RegisterBit Name ="pll_wd_en" StartBit = "9" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      LVDSRX PLL Watch dog enable register:
                       1'b0:disable watch dog;1'b1:enable watch dog
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="test_en" StartBit = "8" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      LVDSRX TEST MODE selection:
                       1'b0:disable test mode;1'b1:enable test mode
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pow" StartBit = "7" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      LVDSRX Power Down register:
                       1'b0: LVDSRX Power Down;1'b1: LVDSRX normal work
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="mode_sel" StartBit = "6" BitCount = "1" RW = "2" default = "3">
                     <![CDATA[ 
                      LVDSRX Mode selection register:
                       00:6bit mode;01:8bit mode;11:10bit mode;10:forbidden
                     ]]>
                 </RegisterBit>
             </Register>
         </RegisterSet>
     </RegisterGroup>
  </Group>
</RegisterBase>

