<?xml version="1.0" encoding="iso8859-1" standalone="yes"?>
<RegisterBase CHIP = "PICASSO">
   <Group Name = "MEMC">
     <RegisterGroup Name = "System">
         <RegisterSet Name = "Display Timing Generator">
             <Register Name = "sc_verid" Address = "0000">
                 <RegisterBit Name ="vercode" StartBit = "31" BitCount = "31" RW = "0" default = "60761010">
                     <![CDATA[ 
                      Chip Version Code
                       
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "sc_lv_rst" Address = "0004">
                 <RegisterBit Name ="porvset_1_0" StartBit = "7" BitCount = "1" RW = "2" default = "0">
                     <![CDATA[ 
                      Low Voltage Reset Detection Level
                       00 : 2.4V
                       01 : 2.6V
                       10 : 2.5V
                       11 : 2.7V
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dummy0004_5_4" StartBit = "5" BitCount = "1" RW = "2" default = "1">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "sc_pol" Address = "0008">
                 <RegisterBit Name ="reset_status" StartBit = "31" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset Status for S/W to detect RESET happened
                       1: Reset to high
                       0: Set low by S/W (write 0)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="boption_status" StartBit = "22" BitCount = "2" RW = "0" default = "0">
                     <![CDATA[ 
                      Bounding options for software.
                       Bit[22]:
                       0x1: 27MHz from crystal (XI, XO) in
                       0x0 : 54 MHz  from (pad_ext54M) in
                       bit[21:20]Package Selection
                       00: LQFP 216
                       01: LQFP 256
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="test_mode_sel" StartBit = "6" BitCount = "2" RW = "0" default = "0">
                     <![CDATA[ 
                      Test mode select:[2:0] = [Pad_gpio_a2, Pad_gpio_a1, Pad_gpio_a0]
                       when test_mode_en_n = 1¡¦b0
                       3¡¦h0: no use
                       3¡¦h1: memc scan mode
                       3¡¦h2: dispd + dispi + top scan mode
                       3¡¦h3: dc sys + phy scan mode
                       3¡¦h7: ECPU mode
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="test_mode_en_n" StartBit = "3" BitCount = "0" RW = "0" default = "1">
                     <![CDATA[ 
                      Test Mode Enable (* Power-On-Latch option(SPI_CS))
                       0: enable Test Mode
                       1: disable Test Mode
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pll_en" StartBit = "2" BitCount = "0" RW = "0" default = "1">
                     <![CDATA[ 
                      PLL Enable (* Power-On-Latch option(SPI_SCLK))
                       when test_mode_en_n = 1'b0
                       0: Disable PLL bypass all pll clock to external input
                       1: Enable PLL
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ctrl_type" StartBit = "1" BitCount = "0" RW = "0" default = "1">
                     <![CDATA[ 
                      Control Type  (* Power-On-Latch option(SPI_SDO))
                       1: I2C
                       0: UART
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="boot_type" StartBit = "0" BitCount = "0" RW = "0" default = "1">
                     <![CDATA[ 
                      Boot Type  (* Power-On-Latch option(IRQ))
                       0: Boot from ROM 
                       1: Boot form External SPI Flash 
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "sys_srst0" Address = "0100">
                 <RegisterBit Name ="dummy0100_19" StartBit = "19" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_r2d" StartBit = "18" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset bit of R2D (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_ddrphi" StartBit = "17" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset bit of DDR PHI (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_dcu" StartBit = "16" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset bit of Dram Control Unit (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_disp" StartBit = "11" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset of Display Domain (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_memc" StartBit = "10" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset of MEMC (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_i" StartBit = "9" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset of I Domain (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_lvds_rx" StartBit = "8" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset of LVDS RX (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dummy0100_7" StartBit = "7" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_timer" StartBit = "6" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset bit of Timer (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_pllreg" StartBit = "5" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset bit of PLL Register (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_padmux" StartBit = "4" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset bit of PAD MUX (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_flash" StartBit = "3" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset bit of FLASH  (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_uart0" StartBit = "2" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset bit of UART0 (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_i2c0" StartBit = "1" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset bit of I2C0 (active low)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn_gpio" StartBit = "0" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reset bit of GPIO (active low)
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "sys_clken0" Address = "0104">
                 <RegisterBit Name ="dummy0104_19" StartBit = "19" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_r2d" StartBit = "18" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Clock Enable of R2D
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_ddrphi" StartBit = "17" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Clock Enable of DDR PHI
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_dcu" StartBit = "16" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Clock Enable of Dram Control Unit 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_disp" StartBit = "11" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Clock Enable of Display Domain 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_memc" StartBit = "10" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Clock Enable of MEMC 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_i" StartBit = "9" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Clock Enable of I Domain 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_lvds_rx" StartBit = "8" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Clock Enable of LVDS RX 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dummy0104_7" StartBit = "7" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_timer" StartBit = "6" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Clock Enable of Timer 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_pllreg" StartBit = "5" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Clock Enable of PLL Register 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_padmux" StartBit = "4" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Clock Enable of PAD MUX 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_flash" StartBit = "3" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Clock Enable of FLASH 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_uart0" StartBit = "2" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Clock Enable of UART0 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_i2c0" StartBit = "1" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Clock Enable of I2C0 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="clken_gpio" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Clock Enable of GPIO 
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "sys_clksel" Address = "0108">
                 <RegisterBit Name ="sys_clksel" StartBit = "0" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      System Clock Source Select
                       0: PLLBUS
                       1: 27MHz XTAL
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "sys_clkdiv" Address = "010C">
                 <RegisterBit Name ="bus_freq_sel" StartBit = "3" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      DBUS Clock Divide Select
                       0: freq = PLLBUS output  (bypass)
                       1: freq = PLLBUS output  / 2
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="cpu_freq_sel" StartBit = "2" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      CPU Clock Divide Select
                       0: freq = DBUS Clock  / 2
                       1: freq = DBUS Clock  / 4
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dummy010c_1" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Dummy
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="flash_freq_sel" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Flash Clock Divide Select
                       0: freq = CPU Clock  / 4
                       1: freq = CPU Clock  / 8
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "sc_debug_0" Address = "0200">
                 <RegisterBit Name ="crt_dbg_sel1" StartBit = "7" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      crt_dbg_out1[15:0] = 16¡¦d0
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="crt_dbg_sel0" StartBit = "3" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      4¡¦d0 : // None
                         crt_dbg_out0 = {14'b0};
                       4¡¦d1 : // rst_n
                         crt_dbg_out0 = {13'b0 , top_all_reg_rst_n };
                       4'd2 : // PLLBUS                                                                       
                         crt_dbg_out0 = {11'b0, top_all_reg_bus_clk_div_out , pllbus_cktst_div_out, pllbus_div_out};  
                       4'd3 : // OTHER                                                                       
                         crt_dbg_out0 = 14'b0                                          
                       4'd4 : // PLLDDR                                                                       
                         crt_dbg_out0 = {6'b0, pllddr_clk_div_out7,pllddr_clk_div_out6,pllddr_clk_div_out5, pllddr_clk_div_out4,pllddr_clk_div_out3,pllddr_clk_div_out2,         
                         pllddr_clk_div_out1,pllddr_clk_div_out0};                            
                       4'd5 : // PLLDISP                                                                      
                         crt_dbg_out0 = {13'b0,plldispd_ckout_div_out};                      
                       4'd6 : // PLL27X                                                                       
                         crt_dbg_out0 = {10'b0,xclk_buf_div_out, xclk27_free_div_out, xclk_div_out, top_all_reg_clk27_div_out};
                       4'd7 : // LVDSRX                                                                       
                         crt_dbg_out0 = {9'b0, lvdsrx_freerun_div_out, lvdsrx_clk1x_e_div_out, lvdsrx_clk1x_o_div_out, lvdsrx_clk2x_e_div_out, lvdsrx_clk2x_o_div_out};
                       4'd8 : // PLLDDR_SSC                                                                      
                         crt_dbg_out0 = {13'b0, ckssc_pllddr_div_out};
                        default : 
                         crt_dbg_out0 = {14¡¦b0};                  
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "sc_debug_1" Address = "0204">
                 <RegisterBit Name ="dbg0_div_sel_7" StartBit = "30" BitCount = "2" RW = "2" default = "0">
                     <![CDATA[ 
                      For crt_dbg_out0[7] divide value selection when used for clock
                       0x0: bypass signal
                       0x1: divided 2
                       0x2: divided by 4
                       0x3: divided by 8
                       0x4: divided by 16
                       0x5: divided by 32
                       Others: bypass
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dbg0_div_sel_6" StartBit = "26" BitCount = "2" RW = "2" default = "0">
                     <![CDATA[ 
                      the same as above description but for crt_dbg_out0[6]
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dbg0_div_sel_5" StartBit = "22" BitCount = "2" RW = "2" default = "0">
                     <![CDATA[ 
                      the same as above description but for crt_dbg_out0[5]
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dbg0_div_sel_4" StartBit = "18" BitCount = "2" RW = "2" default = "0">
                     <![CDATA[ 
                      the same as above description but for crt_dbg_out0[4]
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dbg0_div_sel_3" StartBit = "14" BitCount = "2" RW = "2" default = "0">
                     <![CDATA[ 
                      the same as above description but for crt_dbg_out0[3]
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dbg0_div_sel_2" StartBit = "10" BitCount = "2" RW = "2" default = "0">
                     <![CDATA[ 
                      the same as above description but for crt_dbg_out0[2]
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dbg0_div_sel_1" StartBit = "6" BitCount = "2" RW = "2" default = "0">
                     <![CDATA[ 
                      the same as above description but for crt_dbg_out0[1]
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dbg0_div_sel_0" StartBit = "2" BitCount = "2" RW = "2" default = "0">
                     <![CDATA[ 
                      the same as above description but for crt_dbg_out0[0]
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "r2d_addr" Address = "0220">
                 <RegisterBit Name ="wr_mem_en" StartBit = "31" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Write/Read Memory Enable (Auto Clear)
                       0: Disable
                       1: Enable
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="wr_mem_type" StartBit = "30" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Write/Read Memory Type
                       0: Read
                       1: Write
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="wr_mem_start" StartBit = "29" BitCount = "25" RW = "2" default = "0">
                     <![CDATA[ 
                      WR_MEM_START[24:0]
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "r2d_data0" Address = "0224">
                 <RegisterBit Name ="wr_mem_data0" StartBit = "31" BitCount = "31" RW = "2" default = "0">
                     <![CDATA[ 
                      WR_MEM_DATA0[31:0]
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "r2d_data1" Address = "0228">
                 <RegisterBit Name ="wr_mem_data1" StartBit = "31" BitCount = "31" RW = "2" default = "0">
                     <![CDATA[ 
                      WR_MEM_DATA0[63:32]
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "r2d_data2" Address = "022C">
                 <RegisterBit Name ="wr_mem_data2" StartBit = "31" BitCount = "31" RW = "2" default = "0">
                     <![CDATA[ 
                      WR_MEM_DATA0[95:64]
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "r2d_data3" Address = "0230">
                 <RegisterBit Name ="wr_mem_data3" StartBit = "31" BitCount = "31" RW = "2" default = "0">
                     <![CDATA[ 
                      WR_MEM_DATA0[127:96]
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "st_ie0" Address = "0300">
                 <RegisterBit Name ="ie_dcu" StartBit = "11" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Event Enable of DCU
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ie_rb" StartBit = "10" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Event Enable of R Bus
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ie_id" StartBit = "9" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Event Enable of I Domain 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ie_memc" StartBit = "8" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Event Enable of MEMC 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ie_dct" StartBit = "7" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Event Enable of Display Timing Generator 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ie_timer1" StartBit = "6" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Event Enable of Timer1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ie_timer0" StartBit = "5" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Event Enable of Timer0
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ie_uart1" StartBit = "4" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Event Enable of UART1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ie_uart0" StartBit = "3" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Event Enable of UART0 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ie_i2c0" StartBit = "2" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Event Enable of I2C0 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ie_gpio1" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Event Enable of GPIO1 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ie_gpio0" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Event Enable of GPIO0 
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "st_ip0" Address = "0304">
                 <RegisterBit Name ="ip_dcu" StartBit = "11" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Interrupt Pending Bit of DCU
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ip_rb" StartBit = "10" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Interrupt Pending Bit of R Bus
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ip_id" StartBit = "9" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Interrupt Pending Bit of I Domain 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ip_memc" StartBit = "8" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Interrupt Pending Bit of MEMC 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ip_dct" StartBit = "7" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Interrupt Pending Bit of Display Timing Generator 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ip_timer1" StartBit = "6" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Interrupt Pending Bit of Timer1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ip_timer0" StartBit = "5" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Interrupt Pending Bit of Timer0
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ip_uart1" StartBit = "4" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Interrupt Pending Bit of UART1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ip_uart0" StartBit = "3" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Interrupt Pending Bit of UART0
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ip_i2c0" StartBit = "2" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Interrupt Pending Bit of I2C0
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ip_gpio1" StartBit = "1" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Interrupt Pending Bit of GPIO1 
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ip_gpio0" StartBit = "0" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Interrupt Pending Bit of GPIO0 
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "st_ir0" Address = "0308">
                 <RegisterBit Name ="irs_dcu" StartBit = "11" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      DCU Interrupt Route Select to IRQ0~IRQ1
                       0: IRQ0
                       1: IRQ1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="irs_rb" StartBit = "10" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      R Bus Interrupt Route Select to IRQ0~IRQ1
                       0: IRQ0
                       1: IRQ1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="irs_id" StartBit = "9" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      I Domain Interrupt Route Select to IRQ0~IRQ1
                       0: IRQ0
                       1: IRQ1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="irs_memc" StartBit = "8" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      MEMC Interrupt Route Select to IRQ0~IRQ1
                       0: IRQ0
                       1: IRQ1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="irs_dct" StartBit = "7" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Display Timing Generator Interrupt Route Select to IRQ0~IRQ1
                       0: IRQ0
                       1: IRQ1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="irs_timer1" StartBit = "6" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Timer1  Interrupt Route Select to IRQ0~IRQ1
                       0: IRQ0
                       1: IRQ1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="irs_timer0" StartBit = "5" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Timer0  Interrupt Route Select to IRQ0~IRQ1
                       0: IRQ0
                       1: IRQ1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="irs_uart1" StartBit = "4" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      UART1  Interrupt Route Select to IRQ0~IRQ1
                       0: IRQ0
                       1: IRQ1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="irs_uart0" StartBit = "3" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      UART0  Interrupt Route Select to IRQ0~IRQ1
                       0: IRQ0
                       1: IRQ1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="irs_i2c0" StartBit = "2" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      I2C0 Interrupt Route Select to IRQ0~IRQ1
                       0: IRQ0
                       1: IRQ1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="irs_gpio1" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      GPIO1 Interrupt Route Select to IRQ0~IRQ1
                       0: IRQ0
                       1: IRQ1
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="irs_gpio0" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      GPIO0 Interrupt Route Select to IRQ0~IRQ1
                       0: IRQ0
                       1: IRQ1
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "st_ios0" Address = "030C">
                 <RegisterBit Name ="io_polar" StartBit = "31" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Interrupt Output Signal Polarity
                       0: No Invert (low active)
                       1: Invert (high active)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ios_dcu" StartBit = "11" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      DCU Interrupt Output Select
                       0: SELECT
                       1: NOT SELECT
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ios_rb" StartBit = "10" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      R Bus Interrupt Output Select
                       0: SELECT
                       1: NOT SELECT
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ios_id" StartBit = "9" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      I Domain Interrupt Output Select
                       0: SELECT
                       1: NOT SELECT
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ios_memc" StartBit = "8" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      MEMC Interrupt Output Select
                       0: SELECT
                       1: NOT SELECT
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ios_dct" StartBit = "7" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Display Timing Generator Interrupt Output Select
                       0: SELECT
                       1: NOT SELECT
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ios_timer1" StartBit = "6" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Timer1  Interrupt Output Select
                       0: SELECT
                       1: NOT SELECT
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ios_timer0" StartBit = "5" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Timer0  Interrupt Output Select
                       0: SELECT
                       1: NOT SELECT
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ios_uart1" StartBit = "4" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      UART1  Interrupt Output Select
                       0: SELECT
                       1: NOT SELECT
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ios_uart0" StartBit = "3" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      UART0  Interrupt Output Select
                       0: SELECT
                       1: NOT SELECT
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ios_i2c0" StartBit = "2" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      I2C0 Interrupt Output Select
                       0: SELECT
                       1: NOT SELECT
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ios_gpio1" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      GPIO1 Interrupt Output Select
                       0: SELECT
                       1: NOT SELECT
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ios_gpio0" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      GPIO0 Interrupt Output Select
                       0: SELECT
                       1: NOT SELECT
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "pll_ddsr1" Address = "0600">
                 <RegisterBit Name ="pllddr_m" StartBit = "30" BitCount = "6" RW = "2" default = "1c">
                     <![CDATA[ 
                      PLL feedback divider control
                       Divide by ¡§M [6:0]+2¡¨
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_n" StartBit = "21" BitCount = "1" RW = "2" default = "1">
                     <![CDATA[ 
                      PLL reference divider control
                       00: divide by 1
                       01: divide by 2
                       10: divide by 3
                       11: divide by 4
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_rs" StartBit = "19" BitCount = "3" RW = "2" default = "8">
                     <![CDATA[ 
                      Loop filter resistor (RS) select
                       0000: 10.0 k£[
                       0001: 11.0 k£[
                       0010: 12.0 k£[
                       0011: 13.0 k£[
                       0100: 14.0 k£[
                       0101: 15.0 k£[
                       0110: 16.0 k£[
                       0111: 17.0 k£[
                       1000: 18.0 k£[
                       1001: 19.0 k£[
                       1010: 20.0 k£[
                       1011: 21.0 k£[
                       1100: 22.0 k£[
                       1101: 24.0 k£[
                       1110: 26.0 k£[
                       1111: 28.0 k£[
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_cs" StartBit = "14" BitCount = "2" RW = "2" default = "7">
                     <![CDATA[ 
                      Loop filter capacitor (CS) select
                       000: 76.8 pF
                       001: 80.6 pF
                       010: 84.4 pF
                       011: 88.2 pF
                       100: 92.0 pF
                       101: 99.4 pF
                       110: 106.8 pF
                       111: 114.2 pF
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_cp" StartBit = "10" BitCount = "2" RW = "2" default = "1">
                     <![CDATA[ 
                      Loop filter capacitor (CP) select
                       000: 4.8 pF
                       001: 5.6 pF
                       010: 16.4 pF
                       011: 7.2 pF
                       100: 8.0 pF
                       101: 8.8 pF
                       110: 9.6 pF
                       111: 10.4 pF
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_r3" StartBit = "6" BitCount = "2" RW = "2" default = "2">
                     <![CDATA[ 
                      Loop filter resistor (R3) select
                       000: 6.0 k£[
                       001: 7.0 k£[
                       010: 8.0 k£[
                       011: 9.0 k£[
                       100: 10.0 k£[
                       101: 11.0 k£[
                       110: 12.0 k£[
                       111: 14.0 k£[
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_c3" StartBit = "1" BitCount = "1" RW = "2" default = "2">
                     <![CDATA[ 
                      Loop filter capacitor (C3) select
                       00: 1.00 pF
                       01: 1.25 pF
                       10: 1.50 pF
                       11: 2.00 pF
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "pll_ddsr2" Address = "0604">
                 <RegisterBit Name ="pllddr_ip" StartBit = "10" BitCount = "2" RW = "2" default = "3">
                     <![CDATA[ 
                      Charge-pump current select
                       000: 2.5 uA
                       001: 5.0 uA
                       010: 7.5 uA
                       011: 10.0uA
                       100: 12.5uA
                       101: 15.0uA
                       110: 17.5uA
                       111: 20.0uA
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_wdrst" StartBit = "7" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      PLL watch-dog reset,
                       0: normal
                       1: reset to zero
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_wdset" StartBit = "6" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      PLL watch-dog set
                       0: normal
                       1: set to one
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_psen" StartBit = "5" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Phase shifter enable control (for SSC)
                       0: disable
                       1: enable
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_pstst" StartBit = "3" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Phase shifter test mode control
                       0: normal
                       1: test mode
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_oeb" StartBit = "2" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      CLK_PLLDDR [0] output enable control
                       0: enable
                       1: disable
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_rstb" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      PLL reset control
                       0: reset
                       1: normal
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_pwdn" StartBit = "0" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      PLL power down control
                       0: power on
                       1: power down
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "pll_ddsr3" Address = "0608">
                 <RegisterBit Name ="pllddr_sel0" StartBit = "31" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      CLK_PLLDDR [0] phase select
                       0000:  0/16 phase
                       0001:  1/16 phase
                       0010:  2/16 phase
                       0011:  3/16 phase
                       0100:  4/16 phase
                       0101:  5/16 phase
                       0110:  6/16 phase
                       0111:  7/16 phase
                       1000:  8/16 phase
                       1001:  9/16 phase
                       1010: 10/16 phase
                       1011: 11/16 phase
                       1100: 12/16 phase
                       1101: 13/16 phase
                       1110: 14/16 phase
                       1111: 15/16 phase
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_sel1" StartBit = "27" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      CLK_PLLDDR [1] phase select
                       0000:  0/16 phase
                       0001:  1/16 phase
                                   -
                                   -
                       1110: 14/16 phase
                       1111: 15/16 phase
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_sel2" StartBit = "23" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      CLK_PLLDDR [2] phase select
                       0000:  0/16 phase
                       0001:  1/16 phase
                                   -
                                   -
                       1110: 14/16 phase
                       1111: 15/16 phase
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_sel3" StartBit = "19" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      CLK_PLLDDR [3] phase select
                       0000:  0/16 phase
                       0001:  1/16 phase
                                   -
                                   -
                       1110: 14/16 phase
                       1111: 15/16 phase
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_sel4" StartBit = "15" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      CLK_PLLDDR [4] phase select
                       0000:  0/16 phase
                       0001:  1/16 phase
                                   -
                                   -
                       1110: 14/16 phase
                       1111: 15/16 phase
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_sel5" StartBit = "11" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      CLK_PLLDDR [5] phase select
                       0000:  0/16 phase
                       0001:  1/16 phase
                                   -
                                   -
                       1110: 14/16 phase
                       1111: 15/16 phase
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_sel6" StartBit = "7" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      CLK_PLLDDR [6] phase select
                       0000:  0/16 phase
                       0001:  1/16 phase
                                   -
                                   -
                       1110: 14/16 phase
                       1111: 15/16 phase
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_sel7" StartBit = "3" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      CLK_PLLDDR [7] phase select
                       0000:  0/16 phase
                       0001:  1/16 phase
                                   -
                                   -
                       1110: 14/16 phase
                       1111: 15/16 phase
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "pll_ddsr4" Address = "060C">
                 <RegisterBit Name ="pllddr_ckdcc" StartBit = "13" BitCount = "5" RW = "2" default = "10">
                     <![CDATA[ 
                      CLK_PLLDDR [7:0] duty cycle control
                       MSB = 0
                       000000: 48 %
                                -
                                -
                       010000: 50 %
                                -
                                -
                       011111: 52 %
                       
                       MSB = 1
                       100000: 47 %
                                -
                                -
                       110000: 50 %
                                -
                                -
                       111111: 53 %
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "sc_ddrpll_ssc" Address = "0610">
                 <RegisterBit Name ="ddr_ssc_sse" StartBit = "31" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Spread Spectrum Enable
                       0: disable
                       1: enable
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_fupdn" StartBit = "30" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Frequency up/down control from digital SSC of ddr PLL
                       0: up 
                       1: down
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ddr_ssc_sss" StartBit = "29" BitCount = "5" RW = "2" default = "0">
                     <![CDATA[ 
                      Spread Spectrum Step
                       Unit: PLL BUS target frequency/32/1096
                       0-0 unit
                       1-1 unit
                       ¡K
                       63-63 units
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ddr_ssc_ssn" StartBit = "22" BitCount = "6" RW = "2" default = "0">
                     <![CDATA[ 
                      Spread Spectrum Period
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ddr_ssc_ssfpv" StartBit = "15" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      Spread spectrum frequency peak value offset
                       Unit: PLL BUS target frequency/32/256
                       0 ¡V 0 unit
                       1 ¡V 1 unit
                       ¡K
                       0xFF: -255 unit
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ddr_ssc_stms" StartBit = "1" BitCount = "1" RW = "2" default = "0">
                     <![CDATA[ 
                      Test mode select
                       00: normal
                       01: frequency by M/N code
                       10: 63/64 M/N frequency (-1/64 target frequency)
                       11: 62/64 frequency (-1/32 target frequency)
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "pll_bus1" Address = "0620">
                 <RegisterBit Name ="pllbus_m" StartBit = "30" BitCount = "6" RW = "2" default = "11">
                     <![CDATA[ 
                      M (feedback) divider control 
                       (divide by M [6:0]+2)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllbus_n" StartBit = "21" BitCount = "1" RW = "2" default = "1">
                     <![CDATA[ 
                      N (reference) divider control
                       00: divide by 1
                       01: divide by 2 (default)
                       10: divide by 3
                       11: divide by 4
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllbus_wdrst" StartBit = "13" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      PLL watch dog reset
                       0: normal (default), 1: reset to zero
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllbus_wdset" StartBit = "12" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      PLL watch dog set
                       0: normal (default), 1: set to one
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllbus_rs" StartBit = "11" BitCount = "2" RW = "2" default = "5">
                     <![CDATA[ 
                      Loop filter resistor (RS) select
                       000: 16 k£[
                       001: 18 k£[
                       010: 20 k£[ 
                       011: 22 k£[
                       100: 24 k£[
                       101: 26 k£[(default)
                       110: 28 k£[
                       111: 30 k£[
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllbus_cp" StartBit = "8" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Loop filter capacitor (CP) select
                       0: 1.9 pF (default)
                       1: 2.3 pF
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllbus_ip" StartBit = "7" BitCount = "1" RW = "2" default = "1">
                     <![CDATA[ 
                      Charge-pump current select
                       00: 2.5 uA
                       01: 5.0 uA (default)
                       10: 7.5 uA
                       11: 10.0 uA
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllbus_cs" StartBit = "5" BitCount = "1" RW = "2" default = "3">
                     <![CDATA[ 
                      Loop filter capacitor (CS) select
                       00: 18 pF
                       01: 20 pF
                       10: 24 pF 
                       11: 28 pF (default)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllbus_oeb" StartBit = "3" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      CLK_PLLBUS output enable control
                       0: enable 
                       1: disable
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllbus_rstb" StartBit = "2" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      PLL reset control
                       0: reset 
                       1: normal
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllbus_pwdn" StartBit = "1" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      PLL power down control
                       0: active
                       1: power down
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllbus_tst" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      VCO test clock output enable
                       0: disable (default), 1: enable
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "pll_disp0" Address = "0630">
                 <RegisterBit Name ="dpllqm_9_0" StartBit = "29" BitCount = "9" RW = "2" default = "2c">
                     <![CDATA[ 
                      DPLL DPM value ¡V 2
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllpwdn" StartBit = "19" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      DPLL power down (active high)
                       0:
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllfreeze" StartBit = "18" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      DPLL Output Freeze
                       0:Normal 1:Freeze (active high)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllo_1_0" StartBit = "17" BitCount = "1" RW = "2" default = "0">
                     <![CDATA[ 
                      DPLL Output divider
                       00:Div1, 01:Div2, 10:Div4, 11:Div8
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllqn_7_0" StartBit = "15" BitCount = "7" RW = "2" default = "3">
                     <![CDATA[ 
                      DPLL DPN value ¡V 2
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllvr_1_0" StartBit = "7" BitCount = "1" RW = "2" default = "2">
                     <![CDATA[ 
                      DPLL Loop Filter Resister Control
                       LPFMODE=0, 00:16K, 01:18K, 10:20K, 11:22K
                       LPFMODE=1, 00:46K, 01:53K, 10:60K, 11:67K
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllsi_5_0" StartBit = "5" BitCount = "5" RW = "2" default = "2a">
                     <![CDATA[ 
                      DPLL_CRNT[4:0] = DPLLSI[4:0]
                       I=(2.5uA+2.5uA*bit[0]+5uA*bit[1]+10uA*bit[2]+20uA*bit[3]+30uA*bit[4]) , Ip=I*[(bit[5]+1) / 2]
                       Keep Icp/DPM constant
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "pll_disp1" Address = "0634">
                 <RegisterBit Name ="plldisp_rstb" StartBit = "15" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Reset PLL_DISP
                       0: reset
                       1: normal
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllwdrst" StartBit = "14" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      DPLL WD Reset
                       0:Normal
                       1:Reset
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllwdset" StartBit = "13" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      DPLL WD Set
                       0:Normal
                       1:Set
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllwdvset" StartBit = "12" BitCount = "1" RW = "2" default = "2">
                     <![CDATA[ 
                      DPLL WD Voltage Set
                       00:0.58V
                       01:0.74V
                       10:0.88V
                       11:1.17V
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllfupdn" StartBit = "10" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      DPLL Freqency Tuning
                       1:FreqDn
                       0:FreqUp
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllstop" StartBit = "9" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      DPLL Frequency Tuning
                       1:Enable
                       0:Disable
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dplllpfmode" StartBit = "8" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      DPLL LPF Mode
                       DPN<=5  =>  LPFMode=0  Ich=27.5uA  DPM=46    DPN=5
                       DPN>=5  =>  LPFMode=1  Ich=6.25uA  DPM=110  DPN=12
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllinsel" StartBit = "3" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      0: Xtal (default)
                       1: I Domain Clock
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllbpn" StartBit = "2" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      DPLLBPN=1, N divder disable , OUT=ckxtal
                       DPLLBPN=0 , N divder enable
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllallpwdn" StartBit = "1" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Power Down ALL PLL (active high)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dpllreserve" StartBit = "0" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Reserved for DPLL phase swallow circuit
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "dclkss" Address = "0638">
                 <RegisterBit Name ="dummy0638_31_28" StartBit = "31" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dclk_offset" StartBit = "27" BitCount = "11" RW = "2" default = "0">
                     <![CDATA[ 
                      DCLK Offset in Fixed Last Line DVTOTAL & DHTOTAL
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dclk_new_en" StartBit = "15" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      DDS Spread Spectrum New Mode Enable
                       0: Disable
                       1: Enable
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dclk_ss_test" StartBit = "14" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      DDS Spread Spectrum Test Enable
                       0: Disable
                       1: Enable
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dclk_freq_syn_slt" StartBit = "13" BitCount = "5" RW = "2" default = "0">
                     <![CDATA[ 
                      Frequency Synthesis Select (F & F-N*dF)
                       0: N=1
                       1: N=3
                       2: N=5
                       3: N=7
                       .
                       .
                       63: N=64
                       dF=DCLK/(2^15)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dclk_ss_rag" StartBit = "7" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      DCLK Spreading range (0.0~7.5%)
                       0000: 0.0%
                       0001: 0.5%
                       0010: 1.0%
                       0011: 1.5%
                       0100: 2.0%
                       0101: 2.5%
                       0110: 3.0%
                       0111: 3.5%
                       1000: 4.0%
                       1001: 4.5%
                       1010: 5.0%
                       1011: 5.5%
                       1100: 6.0%
                       1101: 6.5%
                       1110: 7.0%
                       1111: 7.5%
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dummy0638_3" StartBit = "3" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dclk_ss_load" StartBit = "2" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Spread Spectrum Setting Load (Auto Clear)
                       0: Not available
                       1: Load in
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dummy0638_1" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="dclk_ss_en" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Enable DDS Spread Spectrum Output Function
                       0: Disable
                       1: Enable
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "dpll_tracking_ctrl0" Address = "0640">
                 <RegisterBit Name ="dclk_ss_fmdiv" StartBit = "24" BitCount = "4" RW = "2" default = "1">
                     <![CDATA[ 
                      Spread Spectrum FMDIV
                       Period: 2046*4*dpll_period*4/(Dclk_ss_fmdiv)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="m_slow_modify_pixel" StartBit = "19" BitCount = "15" RW = "2" default = "0">
                     <![CDATA[ 
                      As input m code changed, how many dpllfdds clock m code +/-1.
                       Unit: dpll_period*4 clock period.
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="offset_slow_modify_en" StartBit = "2" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      As input m code changed, applied offset will be slowly changed to zero, .
                       0: immediately change to zero, as input m code changed.
                       1: offset slow modify to zero, then slow modify to input offset as input m code changed.
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="m_slow_modify_en" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      As input m code changed, applied m code will be slowly changed.
                       0: disable
                       1: enable
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="tracking_en" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Tracking function enable
                       D domain vs and fll tracking result applied.
                       0: disable
                       1: enable
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "dpll_tracking_ctrl1" Address = "0644">
                 <RegisterBit Name ="m_add_upper_th" StartBit = "26" BitCount = "10" RW = "2" default = "0">
                     <![CDATA[ 
                      Limit the m code add upper bound from d domain result.
                       Signed(11,0)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="m_add_lower_th" StartBit = "10" BitCount = "10" RW = "2" default = "0">
                     <![CDATA[ 
                      Limit the m code add lower bound from d domain result.
                       Signed(11,0)
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "pll_wdout" Address = "06F0">
                 <RegisterBit Name ="dpllstatus" StartBit = "2" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      DPLL WD Status register
                       0:Normal
                       1:Abnormal
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllbus_wdout" StartBit = "1" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      PLL BUS watch dog output
                       0: normal
                       1: abnormal
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="pllddr_wdout" StartBit = "0" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      PLL DDR watch dog status
                       0: normal
                       1: abnormal
                     ]]>
                 </RegisterBit>
             </Register>
         </RegisterSet>
     </RegisterGroup>
  </Group>
</RegisterBase>

