 rtd_inl(0xb8060000);			//61690007: Ver.C

 
 rtd_outl(0xb8060050, 0x00000001);       //BUS clock source select  : 27Mhz crystal		
 rtd_outl(0xb8000200, 0x00000001);       //SCPU clock source select 1: 27Mhz crystal 		
 rtd_outl(0xb8000204, 0x00000001);       //Main UART Clock Source Selec : 27MHz (XTAL)		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb801a808, 0x0000000b);       //12.10	Serial Flash Controller register	
 rtd_outl(0xb801a814, 0x00000000); 		
 rtd_outl(0xb801a80c, 0x00202020); 		
 rtd_outl(0xb8000400, 0x000b6400);       //5.4.1  SCPU PLL control register	756MHz	
 rtd_outl(0xb8000404, 0x00000005); 		
 rtd_outl(0xb8000404, 0x00000007); 		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8000404, 0x00000003); 		
 rtd_outl(0xb8000480, 0x04ae8b52);       //5.4.6  BUS PLL Control Register		
 rtd_outl(0xb8000488, 0x00000005); 		
 rtd_outl(0xb8000488, 0x00000007); 		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8000488, 0x00000003); 		
 rtd_outl(0xb8000498, 0x00000004);       //PLL BUS HS enable		
 rtd_outl(0xb8000490, 0x04928b52); 		
 rtd_outl(0xb8000498, 0x00000005); 		
 rtd_outl(0xb8000498, 0x00000007); 		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8000498, 0x00000003); 		
 rtd_outl(0xb8000408, 0x0009e400);       //5.4.2  ACPU PLL control register		
 rtd_outl(0xb800040c, 0x00000005); 		
 rtd_outl(0xb800040c, 0x00000007); 		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb800040c, 0x00000003); 		
 rtd_outl(0xb8000410, 0x00005a00);       //5.4.3  VCPU PLL control register		
 rtd_outl(0xb8000414, 0x00000005); 		
 rtd_outl(0xb8000414, 0x00000007); 		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8000414, 0x00000003); 		
 rtd_outl(0xb8000530, 0x00804e90);       //5.4.18  Display PLL Control Register		
 rtd_outl(0xb8000534, 0x0000000d); 		
 rtd_outl(0xb8000534, 0x0000000f); 		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8000534, 0x00000003); 		
		
 rtd_outl(0xb8000464, 0x8c888a08);       //16 to 1 clock mux selection (for VB)		
 rtd_outl(0xb8000460, 0x06a06960);	//DDR PLL control register	648
 rtd_outl(0xb8000470, 0x00000004); 		
 rtd_outl(0xb8000470, 0x00000006); 		
 ScalerTimer_DelayXms(0x00000100);       //short delay		
 rtd_outl(0xb8000470, 0x00000002); 		
		
 rtd_outl(0xb80004a4, 0x000983b0);       //5.4.9  ETN PLL Control Register		
 rtd_outl(0xb80004a8, 0x00000005); 		
 rtd_outl(0xb80004a8, 0x00000007); 		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb80004a8, 0x00000003); 		
 rtd_outl(0xb8000418, 0x0743d2fc);       //5.4.4  PLLDDS/PSAUD Control Register		
 rtd_outl(0xb800041c, 0x000000ff); 		
 rtd_outl(0xb8000424, 0x00000005); 		
 rtd_outl(0xb8000424, 0x00000007); 		
 rtd_outl(0xb8000420, 0x00000005); 		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8000424, 0x00000003); 		
 rtd_outl(0xb8000550, 0x04828b52);       //5.4.19  PLL BUS2 Control Register		
 rtd_outl(0xb8000554, 0x000000ff); 		
 rtd_outl(0xb8000558, 0x00000005); 		
 rtd_outl(0xb8000558, 0x00000007); 		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8000558, 0x00000003); 		
 rtd_outl(0xb8060050, 0x00000001);       //  ST_BUS =27MHz		
 rtd_outl(0xb8060054, 0x00000001);       //		
 rtd_outl(0xb8000200, 0x00000001);       //  SCPU_clk=27M		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8000104, 0xffffffff);       //SYS_RST1 reset de-active		
 rtd_outl(0xb8000108, 0xffffffff);       //SYS_RST2 reset de-active		
 rtd_outl(0xb8000114, 0xffffffff);       //SYS_CLK_EN1 all enable		
 rtd_outl(0xb8000118, 0xffffffff);       //SYS_CLK_EN2 all enable		
 rtd_outl(0xb8060044, 0xffffffff);       // st_ip clk en		
 rtd_outl(0xb8000470, 0x00000004);       //5.4.5  reopen/close DDR PLL control register to solve DC_SYS bug		
 rtd_outl(0xb8000470, 0x00000006); 		
 rtd_outl(0xb8000470, 0x00000002); 		
		
 rtd_outl(0xb8000470, 0x00000006);       //disable DDR PLL output enable control		
 rtd_outl(0xb8000104, 0x31ff9fef); 		
 rtd_outl(0xb8000104, 0x33ff9fef); 		
 rtd_outl(0xb8000470, 0x00000002);       //enable DDR PLL output enable control		
 rtd_outl(0xb800890c, 0x00000131); 		
 rtd_outl(0xb8008b00, 0x0a906417);       //2L setting, E2 off		
 rtd_outl(0xb8008b04, 0x00506417);       //2L setting, E2 off		
 rtd_outl(0xb8008b08, 0x00506417);       //2L setting, E2 off		
 rtd_outl(0xb8008b0c, 0x00506417);       //2L setting, E2 off		
 rtd_outl(0xb8008b34, 0x00492b6d); 		
 rtd_outl(0xb8008b38, 0x00492b6d); 		
 rtd_outl(0xb8008b3c, 0x00492b6d); 		
 rtd_outl(0xb8008b40, 0x00492b6d); 		
 rtd_outl(0xb8008930, 0x24924924);       //dq = 4 ,	dqs= 1	,
 rtd_outl(0xb8008934, 0x24924924); 		
 rtd_outl(0xb8008938, 0x24924924); 		
 rtd_outl(0xb800893c, 0x24924924);       //0x124924a4);		
 rtd_outl(0xb8008004, 0x01421010);       //for 1Gb DDR x 1pcs (128MB)		
 rtd_outl(0xb8008800, 0x66bbbc89);       //Timing setting for 1333 x 1pcs  CL9		
 rtd_outl(0xb8008908, 0x00000007);       //CAL_CTRL Read auto calibration delay tap: 1-3tap, 7-5tap.		
 rtd_outl(0xb8008944, 0x00000229);       //HALF_CYCLE_CAL_EN		
 rtd_outl(0xb800894c, 0x00200000);       //0.75tCK		
 rtd_outl(0xb800891c, 0x00000000);       //new add		
 rtd_outl(0xb800897c, 0x00000001);       //SYNC_RST_FIFO_PT		
 rtd_outl(0xb800897c, 0x00000000);       //SYNC_RST_FIFO_PT		
 rtd_outl(0xb8008828, 0x00ad1f4c);       //DC_MISb CL9	//(modify with Frequency) modify Tmcl/2+bit[0] must equal to TCWL on DDR spec 	
 rtd_outl(0xb8008808, 0x00400a51);       //MOD_REG1 & MOD_REG0	set to CL9 and BC4 + RTT=RZQ/6 + RON=RZQ/6	(modify with Frequency)
 rtd_outl(0xb8008804, 0x00fa4700);       //TMCTRL2		
 rtd_outl(0xb8008804, 0x007a4700);       //TMCTRL2 ??? bit[31:14] define as Rvd?		
 rtd_outl(0xb8008848, 0x000009b8);       //setting from saturn CL9		
 rtd_outl(0xb8008818, 0x4fe0423f);       //2L Ver.B CL9-new		
 rtd_outl(0xb8008844, 0x00000008);       //MOD_REG3 / MOD_REG2 set to CL9 (modify with Frequency)		
 rtd_outl(0xb8008928, 0x0001d2b8);       //set DDR OCD 40,ODT to 60		
 ScalerTimer_DelayXms(0x00000010);       //short delay		
 rtd_inl(0xb800892c) --> 0x8005bda5;       //check ZCTRL calibratoin status		
 rtd_inl(0xb8008a18) --> 0x00000000;       //check ODT calibration result		
 rtd_inl(0xb8008a20) --> 0x0000ffff; 		
 rtd_outl(0xb800884c, 0x00000030);       //same with saturn		
 rtd_outl(0xb8008850, 0x00000000);       //same with saturn		
 rtd_outl(0xb8008904, 0x00001661);       //saturn read latency setting		
 rtd_outl(0xb8008840, 0x30000000);       //same setting with saturn		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8008840, 0x0a000000);       //DC_DDR3_CTL		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8008840, 0x0000c003);       //DC_DDR3_CTL		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8008840, 0x03000000);       //DC_DDR3_CTL		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8008840, 0x0c000000);       //DC_DDR3_CTL		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8008840, 0x00200000);       //ERR_STATUS		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8008880, 0x00000618); 		
 rtd_outl(0xb800882c, 0x03000000);       //apply all RX DQS to DQ delay chain for initial phase		
 rtd_outl(0xb8008954, 0x00000191); 		
 rtd_outl(0xb8008a00, 0x0000ffff);       //pcb.ver.c.corepw115.702M		
 rtd_outl(0xb8008a04, 0x0000ffff);       //pcb.ver.c.corepw115.702M		
 rtd_outl(0xb8008a08, 0x0000ffff);       //pcb.ver.c.corepw115.702M		
 rtd_outl(0xb8008a0c, 0x0000ffff);       //pcb.ver.c.corepw115.702M		
 rtd_outl(0xb8008a10, 0xcccc3333);       //pcb.ver.c.corepw115.702M		
 rtd_outl(0xb8008950, 0x00000000);       //pcb.ver.c.corepw115.702M ,more better,for some pcb must be		
 rtd_outl(0xb8000200, 0x00000000);       //SCPU_clock source selection	0: SCPU_PLL / 1: XTAL27	
 ScalerTimer_DelayXms(0x00000001);       //short delay		
 rtd_outl(0xb8060050, 0x00000000); 		
 ScalerTimer_DelayXms(0x00000001);       //short delay		
		
 rtd_outl(0xb8000200, 0x00000000);       //SCPU clock source select 1: 27Mhz crystal 		
 rtd_outl(0xb8060050, 0x00000000);       //BUS clock source select  : 27Mhz crystal		
 rtd_maskl(0xb8000118, 0xfffbffff, 0x00000000); 		
 rtd_maskl(0xb8000108, 0xffe3ffff, 0x00000000); 		
 rtd_maskl(0xb8000230, 0x00000000, 0x00000000); 		
 ScalerTimer_DelayXms(0x00000100);       //short delay		
 rtd_maskl(0xb8000230, 0xffffffff, 0x0000003d); 		
 ScalerTimer_DelayXms(0x00000200);       //short delay		
 rtd_maskl(0xb8000118, 0xffffffff, 0x00040000); 		
 ScalerTimer_DelayXms(0x00000200);       //short delay		
 rtd_maskl(0xb8000118, 0xfffbffff, 0x00000000); 		
 ScalerTimer_DelayXms(0x00000200);       //short delay		
 rtd_maskl(0xb8000230, 0xffffffff, 0x00000002); 		
 rtd_maskl(0xb8000108, 0xffffffff, 0x001c0000); 		
 ScalerTimer_DelayXms(0x00000200);       //short delay		
 rtd_maskl(0xb8000118, 0xffffffff, 0x00040000); 		
 ScalerTimer_DelayXms(0x00000002);       //short delay		
 rtd_outl(0xb8060040, 0xffffffff);       //ST_CLKEN0		
 rtd_outl(0xb8060044, 0xffffffff);       //ST_CLKEN1		