rtd_outl(0xb801685c,0x841f0001);// change Page to 1
ScalerTimer_DelayXms(10);
rtd_inl(0xb801685c);            //0x041f0001

rtd_outl(0xb801685c,0x8411bcca);// Transmit Compensation capacitor adjustment
ScalerTimer_DelayXms(5);
rtd_inl(0xb801685c);            //0x0411bcca

rtd_outl(0xb801685c,0x841290a8);// Transmit Reference Voltage adjustment
ScalerTimer_DelayXms(5);
rtd_inl(0xb801685c);            //0x041290a8

rtd_outl(0xb801685c,0x84156301);// Receive Curent adjustment
ScalerTimer_DelayXms(5);
rtd_inl(0xb801685c);            //0x04156301

rtd_outl(0xb801685c,0x841f0004);// change Page to 4
ScalerTimer_DelayXms(10);
rtd_inl(0xb801685c);            //0x041f0004

rtd_outl(0xb801685c,0x841c0400);
ScalerTimer_DelayXms(5);
rtd_inl(0xb801685c);            //0x041c0400

rtd_outl(0xb801685c,0x841c0bff);
ScalerTimer_DelayXms(5);
rtd_inl(0xb801685c);            //0x041c0bff

rtd_outl(0xb801685c,0x841d0000);
ScalerTimer_DelayXms(5);
rtd_inl(0xb801685c);            //0x041d0000

rtd_outl(0xb801685c,0x841d0001);
ScalerTimer_DelayXms(5);
rtd_inl(0xb801685c);            //0x041d0001

rtd_outl(0xb801685c,0x841d0003); //wait 400us
ScalerTimer_DelayXms(6);
rtd_inl(0xb801685c);            //0x041d0003

rtd_outl(0xb801685c,0x041d0000);//Check the SRAM ROM BIST DONE is 0x0C03 (Pass Criterion 1)
ScalerTimer_DelayXms(5);
rtd_inl(0xb801685c);            //0x841d0C03

rtd_outl(0xb801685c,0x841d0013);
ScalerTimer_DelayXms(5);
rtd_inl(0xb801685c);            //0x041d0013

rtd_outl(0xb801685c,0x041d0000);//Check the ROM MISR value is 0x1115 (Pass Criterion 2)
ScalerTimer_DelayXms(5);
rtd_inl(0xb801685c);            //0x841dE09B check_sum 0xE09B
ScalerTimer_DelayXms(5);
