+q  // Enter quiet mode
+mon
//________________________________________________________
// startice.cmd: Created by MAJIC Setup Wizard version 3.3 
// Creation Date: 11/1/2004 19:51:11
// Processor type: LX5280 -v5280
// Project: DVR
// Description: ACPU or VCPU (Lexra 5280)
//________________________________________________________
dv "Reading startice.cmd file\n"
//
// Software Settings
//
eo semi_hosting_enabled= on   // Semihosting support
//
// Target Information Options
//
eo trgt_resets_jtag  = no   // Target reset does not reset JTAG controller
//
// MAJIC Settings
//
eo ice_jtag_clock_freq= 16   // JTAG clock frequency (MHz)
eo ice_jtag_use_trst  = off  // Controls whether MAJIC drives the TRST* signal
eo ice_reset_output   = off  // reset command does not pulse MAJICs reset output
eo ice_power_sense    = RST // Sense target voltage level on TRST pin
eo Ice_Jtag_Tap_Select = 2		// 2: LX4181(MCPU) ; 1:LX5280(AVCPU)

//
// Trace aliases (MAJIC-Plus or MAJIC-mx only)
//
//ea dts  do ice_trig*; do trace*  // display trace control settings
//ea kts  eo tt=auto; eo tta=stop; eo tg=none; // kill trace settings (set defaults)
//ea etf_asid etf tpoint m=f e=y ia=location bb=1 ba=1  // display ASID in trace window
//
//
//ea CP1 eo Ice_Jtag_Tap_Select = 1 // Select control processor
//ea CP2 eo Ice_Jtag_Tap_Select = 2 // Select I/O processor #1
dv "Finished reading startice.cmd\n"
//-mon

//=================================================================================================
dv "Initial PLL Settings\n"

//================================================================================================
//Initialize all PLLs

//ew 0xb8000200 = 0x00000003					//Switch to 27MHz
//ew 0xb8000600 = 0x0e100a74  				//PLL_CPU1: 27*16/2 = 216MHz (AVCPU)
//ew 0xb8000620 = 0x05187122					//PLL_DDR1: 27*16/2 = 216MHz 
											//- MCPU Freq = 108MHz
											//- Bus Freq = 108MHz
											//- DDR Freq = 216MHz

//================================================================================================
ew 0xb8000650 = 0xb6b0f040					//PLL27X	
ew 0xb8000660 = 0x05288040					//PLLAUD_PS
ew 0xb8000664 = 0x001ec230					//PLL512_FS
	
//================================================================================================
//ew 0xb8000628 = 0x8d228828//0x8ca888a8   	//PLL_DDSR3		
ew 0xb8000628 = 0x8c228828//0x8ca888a8   	//PLL_DDSR3	
ew 0xb8000624 = 0x00000304   				//Power On for PLLDDR		
ew 0xb8000624 = 0x00000306   				//Release Reset for PLLDDR
ew 0xb8000624 = 0x00000302   				//Output Enable for PLLDDR

//================================================================================================
//ew 0xb8000694 = 0x00001151					//PLLDDS1
//ew 0xb80006d0 = 0x169510a1   				//PLLDIF

//================================================================================================
//ew 0xb8000640 = 0x2c03aa96					//PLL_DISP0
//ew 0xb8000644 = 0x00001600   				//PLL_DISP1 reset
//ew 0xb8000644 = 0x00009600   				//PLL_DISP1 normal
	
#//================================================================================================
											//Select Bus PLL as System Clock
											//Register SYS_CPUCLKSEL (0xB8000200)
											//- IO[31:2]: Reserved 
											//- IO[1]: BUS_CLKSEL    
											//		 	BUS clock source select  
											//			- 0: DDR PLL
											//			- 1: 27Mhz crystal
											//- IO[0]: SCPU_CLKSEL
											//  		SCPU and VCPU clock source select 
											//			- 0: CPU PLL
											//			- 1: 27Mhz crystal 
   	
ew 0xB8000200 = 0x00000002					//Switch CPU Clock
ew 0xB8000200 = 0							//Switch Bus Clock

//================================================================================================
//Reset & Clock Enable
											//Reset for All IPs
//ew 0xB8000108 = 0							//SYS_SRST2 
//ew 0xB800010c = 0							//SYS_SRST3
	
											//Enable Clock for Some IPs
//ew 0xB8000114 = 0xFFFFFFFF					//SYS_CLKEN1
//ew 0xB8000118 = 0xFFFFFFFF					//SYS_CLKEN3
	
											//Disable Clock for All IPs
//ew 0xB8000114 = 0							//SYS_CLKEN1
//ew 0xB8000118 = 0							//SYS_CLKEN3

											//Release Reset for All IPs
ew 0xB8000108 = 0xFFFFFFFF					//SYS_SRST2
ew 0xB800010c = 0xFFFFFFFF					//SYS_SRST3

											//Register SYS_CLKEN1 (0xB8000114)
											//- IO[31]: Reserved                                    
											//- IO[30]: CLKEN_SB3: Clock enable bit for SB3                                      
											//- IO[29]: Reserved                                     
											//- IO[28]: CLKEN_SB0: Clock enable bit for SB0                                      
											//- IO[27]: CLKEN_IF_DEMOD: Clock enable for if_demod                                     
											//- IO[26]: CLKEN_VDEC: Clock enable for video decoder                                
											//- IO[25]: Reserved                                    
											//- IO[24]: CLKEN_DCU: Clock enable bit for DCU                                      
											//- IO[23]: CLKEN_AUDIO_PRE512FS: Clock enable for audio Audio_pre512fs                         
											//- IO[22]: CLKEN_AUDIO_DAAD_256FS: Clock enable for Audio_daad_256fs                                                        
											//- IO[21]: CLKEN_AUDIO_DAAD_128FS: Clock enable for Audio_daad_128fs                                                  
											//- IO[20]: CLKEN_AUDIO: Clock enable for Audio Decoder, including BBADC/BBDAC                                                               
											//- IO[19]: Reserved                             
											//- IO[18]: Reserved         
											//- IO[17]: Reserved                                                                                     
											//- IO[16]: CLKEN_ETN: Clock enable bit for ETN                                                                            
											//- IO[15]: CLKEN_USB: Clock enable bit for USB                                                                                                       
											//- IO[14]: Reserved                                     
											//- IO[13]: Reserved                                
											//- IO[12]: CLKEN_VBIS0: Clock enable bit for VBI0 Slicer                                 
											//- IO[11]: CLKEN_DISPD: Clock enable bit for display d_domain                            
											//- IO[10]: CLKEN_DISPM: Clock enable bit for display m_domain                            
											//- IO[9]: CLKEN_DISPI: Clock enable bit for display i_domain / off line measure / ADC   
											//- IO[8]: CLKEN_HDMIG: Global Clock enable for hdmi rx (rbus_clock enable)              
											//- IO[7]: CLKEN_HDMI: Clock enable for HDMI rx except rbus_clock                       
											//- IO[6]: CLKEN_TP: Clock enable bit for TP                                         
											//- IO[5]: Reserved                                          
											//- IO[4]: Reserved                                         
											//- IO[3]: CLKEN_MVD: Clock enable bit for MVD                                          
											//- IO[2]: Reserved                                          
											//- IO[1]: Reserved                                          
											//- IO[0]: Reserved                                          
ew 0xB8000114 = 0xFFFFFFFF

											//Register SYS_CLKEN3 (0xB8000118)
											//- IO[31]: CLKEN_PERI: Clock enable of Peripheral (rbus wrapper of bus/98MHz domain)                                    
											//- IO[30]: CLKEN_PIN_MUX: Clock enable of Pin Mux                                  
											//- IO[29]: CLKEN_GPIO: Clock enable of GPIO                                         
											//- IO[28]: CLKEN_IRDA: Clock enable of IRDA                                         
											//- IO[27]: CLKEN_I2C1: Clock enable of I2C1                                   
											//- IO[26]: CLKEN_I2C2: Clock enable of I2C2  
											//- IO[25]: Reserved                                   
											//- IO[24]: CLKEN_TIMER: Clock enable of Timer                                        
											//- IO[23]: CLKEN_DDC: Clock enable of DDC                                          
											//- IO[22]: CLKEN_SFC: Clock enable of Spi Flash                                    
											//- IO[21]: CLKEN_LSADC: Clock enable of LSADC                                        
											//- IO[20]: CLKEN_UART0: Clock enable of UART0                                        
											//- IO[19]: CLKEN_UART1: Clock enable of UART1                                        
											//- IO[18]: CLKEN_UART2: Clock enable of UART2
											//- IO[17]: CLKEN_UART3: Clock enable of UART3
											//- IO[16]: CLKEN_SC: Clock enable of Smart Card                                 
											//- IO[15]: Reserved                                   
											//- IO[14]: Reserved                                  
											//- IO[13]: CLKEN_M2M: Clock enable of Memory DMA                                          
											//- IO[12]: CLKEN_ROTDMA: Clock enable of Rotation DMA 
 											//- IO[11]: CLKEN_CR: Clock enable of Card Reader                                      
											//- IO[10]: CLKEN_JPEG: Clock enable of JPEG                                     
											//- IO[9]: Reserved                                      
											//- IO[8]: Reserved                                                          
											//- IO[7]: Reserved            
											//- IO[6]: Reserved                                                                                     
											//- IO[5]: CLKEN_LX_BCTL1: Clock enable of LX_BTCL1   
											//- IO[4]: CLKEN_LX_BCTL0: Clock enable of LX_BTCL0                                                                                      
											//- IO[3]: CLKEN_NF: Clock enable for NAND Flash 
											//- IO[2]: CCLKEN_AUDIO2_512FS: Clock enable for audio path 2 Audio_512fs                                          
											//- IO[1]: RCLKEN_AUDIO2_DAAD_256FS: Clock enable for audio path 2 Audio_daad_256fs                                           
											//- IO[0]: RCLKEN_AUDIO2_DAAD_128FS: Clock enable for audio path 2 Audio_daad_128fs                                          
ew 0xB8000118 = 0xFFFFFFFF	

//================================================================================================
//Initial DCU (Las Vegas)

//ew 0xb8008004 = 0x000a0000                  //Page Size = 2048 byte, Disable Picture Offset, Select DDR2 PHY


ew 0xb8008004 = 0x00092020
ew 0xb80089ac = 0x00037b61					//Dummy Pad
ew 0xb80088dc = 0x00032b61					//DCK
ew 0xb80088e4 = 0x00032b61					//DAD12
ew 0xb80088e0 = 0x00032b61					//CKE
ew 0xb80088d0 = 0x00037b61					//DQS1
ew 0xb8008934 = 0x00037b61					//DQS0
ew 0xb80088d4 = 0x00032b61					//DM1
ew 0xb8008930 = 0x00032b61					//DM0
ew 0xb80088b0 = 0x00037b61					//DQ15
ew 0xb80088b4 = 0x00037b61					//DQ14
ew 0xb80088b8 = 0x00037b61					//DQ13
ew 0xb80088bc = 0x00037b61					//DQ12
ew 0xb80088c0 = 0x00037b61					//DQ11
ew 0xb80088c4 = 0x00037b61					//DQ10
ew 0xb80088c8 = 0x00037b61					//DQ9
ew 0xb80088cc = 0x00037b61					//DQ8
ew 0xb8008938 = 0x00037b61					//DQ7
ew 0xb800893c = 0x00037b61					//DQ6
ew 0xb8008940 = 0x00037b61					//DQ5
ew 0xb8008944 = 0x00037b61					//DQ4
ew 0xb8008948 = 0x00037b61					//DQ3
ew 0xb800894c = 0x00037b61					//DQ2
ew 0xb8008950 = 0x00037b61					//DQ1
ew 0xb8008954 = 0x00037b61					//DQ0



//Initial DDR2 PHY
//ew 0xb8008800 = 0x66a22247                  //Initial Related Timing Setting of DRAM (columbus)
//ew 0xb80089C0 = 0x55555555					//columbus
//ew 0xb8008800 = 0x26a22247				//LV
//ew 0xb8008820 = 0x0c0c0c0c
//ew 0xb8008828 = 0x00699668
//ew 0xb8008810 = 0xfffffffe
//ew 0xb8008808 = 0x04000a52
//ew 0xb8008804 = 0x007a0700
//ew 0xb8008818 = 0x00000a00
//ew 0xb800881c = 0xb0000b00
//ew 0xb800882c = 0x03044c0c 					// columbus
//ew 0xb800882c = 0x03044410 			    // LV
//ew 0xb800880c = 0x00000010






ew 0xb8008004 = 0x000a0000                  //Page Size = 2048 byte, Disable Picture Offset, Select DDR2 PHY
ew 0xb8008800 = 0x66a22247                  //Initial Related Timing Setting of DRAM
ew 0xb80089C0 = 0x55555555
ew 0xb8008820 = 0x0C0C0C0C                  //Set Specific Number of Delay Chain
ew 0xb8008828 = 0x00699668                  //Initial Related Timing Setting of DRAM
ew 0xb8008810 = 0xFFFFFFFE                  //Set Row and Column of Calibration Address
ew 0xb8008808 = 0x00000A52                  //Set DRAM Mode to Sequential, Burst = 4 and CAS = 1.5 Cycles
ew 0xb8008804 = 0x007A0700                  //Set DRAM Calibration with User Delay Chain Setting
ew 0xb8008818 = 0x00000A00                  //Set CAS Latency of DRAM Read Block to 5 Cycles
ew 0xb800881C = 0xB0000B00                  //Initial Related DLL Setting of DRAM
ew 0xb800882C = 0x03044493                  //Set Specific Number of Delay Chain
ew 0xb800880c = 0x00000010                  //Start to DRAM Initialization




//================================================================================================
//Pinmux

//ew 0xB8000830 = 0x24842400					//UART0_RX_5
//ew 0xB8000878 = 0x24747400					//DDC3 / UART1_RX_3 / UART3_RX_1
//ew 0xB80008C0 = 0x000000B5					//NAND_0, UART0_RX_5, UART1_RX_3, UART3_RX_1

//================================================================================================
//_Package_LQFP256_N3D:
//_Package_LQFP256_NE2D:
ew 0xB8000808 = 0							//PB4 = 0, PB5 = 0, PB6 = 0, PB7 = 0
//ew 0xB8000838 = 0x34040404					//PH4 = 0, PH5 = 0, PH6 = 0
ew 0xB800084C = 0x04000404					//PJ0 = 0, PJ1 = 0, PJ3 = 0
ew 0xB8000848 = 0x04040404					//PJ4 = 0, PJ5 = 0, PJ6 = 0, PJ7 = 0
ew 0xB8000850 = 0x04242400					//PK7 = 0
ew 0xB800091c = 0xFc000000					//Enable LVDS Power

//================================================================================================
//_Package_LQFP256_NED4LVDS:
//ew 0xB80008C0 = 0x000004B5					//NAND_1, UART0_RX_5, UART1_RX_3, UART3_RX_1
//ew 0xB8000838 = 0x34040434					//PH5 = 0, PH6 = 0	
//ew 0xB8000864 = 0x04040404					//PM0 = 0, PM1 = 0, PM2 = 0, PM3 = 0	
//ew 0xB8000860 = 0x02040404					//PM4 = 0, PM5 = 0, PM6 = 0
//ew 0xB8000868 = 0x04040404					//PN4 = 0, PN5 = 0, PN6 = 0, PN7 = 0
//ew 0xB8000870 = 0x00040424					//PO5 = 0, PO6 = 0
//ew 0xB800091c = 0xF0000000					//Enable LVDS Power

//================================================================================================

// End of File