<?xml version="1.0" encoding="iso8859-1" standalone="yes"?>
<RegisterBase CHIP = "Picasso">
   <Group Name = "CPU">
     <RegisterGroup Name = "EMCU">
         <RegisterSet Name = "EMCU">
             <Register Name = "imem4k_addr" Address = "0500">
                 <RegisterBit Name ="addr" StartBit = "3" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      Start address [15:12] of IMEM, start address should be 4K boundary.
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "imem4k_bank" Address = "0501">
                 <RegisterBit Name ="bank" StartBit = "7" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      8-bit bank info
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "imem4k_remap" Address = "0502">
                 <RegisterBit Name ="done" StartBit = "1" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      remap done
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="remap" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      1:map program from serial flash to IMEM
                       0:stop mapping
                       Don¡¦t clear remap in IMEM region
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "global_mapping" Address = "0503">
                 <RegisterBit Name ="4k_map" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Asserting this bit, we map program of imem_4k_addr in all bank to 4k IMEM. Source of 4k IMEM will be choosed by register imem4k_bank.
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "imem4k_nonstop_dma" Address = "0504">
                 <RegisterBit Name ="enable" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      enable =1; while CPU process IMEM code, then we could do DMA without stop CPU
                       enable =0:we always gated CPU clk, while DMA is triggered
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "wait_cycle" Address = "0510">
                 <RegisterBit Name ="wait_cycle_en" StartBit = "7" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      enable wait cycle function
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="wait_cycle" StartBit = "4" BitCount = "4" RW = "2" default = "0">
                     <![CDATA[ 
                      When R-bus access 8-bit registers, we could wait a specify ¡§wait_cycle¡¨. We define this register to descript this function.
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "timeout_ack" Address = "0511">
                 <RegisterBit Name ="cycle" StartBit = "2" BitCount = "1" RW = "2" default = "0">
                     <![CDATA[ 
                      0:64 cycles
                       1:128 cycles
                       2:256 cycles
                       3:512 cycles
                       After those cycles, module doesn¡¦t return ack for read/write. Reg Wrapper will receive the dummy ack to prevent that CPU is hang.
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="enable" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      0:disable this function
                       1:enable this function
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "regwrap" Address = "0512">
                 <RegisterBit Name ="int" StartBit = "0" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      interrupt with write clear out function to detect time out of ack
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "regwrap_ie" Address = "0513">
                 <RegisterBit Name ="enable" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      interrupt enable
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "mcutime" Address = "0514">
                 <RegisterBit Name ="rd_dly_en" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      1: mcurd will be delay 1T
                       0: mcurd assert at original timing.
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="wr_dly_en" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      1: mcuwr will be delay 1T
                       0: mcuwr assert at original timing.
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "register_endian" Address = "0515">
                 <RegisterBit Name ="swap" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      we separate a 32-bit register as 4 ¡§8-bit¡¨ register, 03, 02, 01 and 00. Swap can change the arrangement like below.
                       swap = 0: reg_32 = { 03,02,01,00}
                       swap = 1: reg_32 = { 00,01,02,03}
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "spi_dma_flash_lsb" Address = "0520">
                 <RegisterBit Name ="addr" StartBit = "7" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      flash address.
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "spi_dma_flash_msb" Address = "0521">
                 <RegisterBit Name ="addr" StartBit = "7" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      flash address
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "spi_dma_bank" Address = "0522">
                 <RegisterBit Name ="bank" StartBit = "7" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      8-bit bank info
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "spi_dma_ctrl" Address = "0523">
                 <RegisterBit Name ="mode" StartBit = "3" BitCount = "1" RW = "2" default = "0">
                     <![CDATA[ 
                      mode 0:write 8bit registers only (Not used)
                       mode 1:write dmem
                       mode 2:write Register(Except 8-bits register)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="done" StartBit = "1" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      While done bit assert, the dma process is done. It will be automatically reset When go bit is assert.
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="go" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      to trigger dma function
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "spi_dma_len_lsb" Address = "0524">
                 <RegisterBit Name ="size" StartBit = "7" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      DMEM/reg dma transfer size, unit is 1 byte
                       but for register (mode2), unit is 4 bytes and only [5:0] is availabler.
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "spi_dma_len_msb" Address = "0525">
                 <RegisterBit Name ="size" StartBit = "7" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      DMEM/reg dma transfer size, unit is 1 byte but for register(mode2), unit is 4 bytes
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "spi_dma_dest_lsb" Address = "0526">
                 <RegisterBit Name ="addr" StartBit = "7" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      destination address LSB could be dmem/ regsters
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "spi_dma_dest_msb" Address = "0527">
                 <RegisterBit Name ="addr" StartBit = "7" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      destination address MSB  could be dmem/ registers. This register is uselsee while destination is 8bit registers.
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "rom_ctrl" Address = "0530">
                 <RegisterBit Name ="boot_from_rom" StartBit = "2" BitCount = "0" RW = "0" default = "1">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="boot_rom" StartBit = "1" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      When MCU bootup, MCU execute ROM code to program SPI. If programming is done, MCU set this bit low and reset MCU. In next time, MCU will boot from SPI.
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rom_wr" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "dummy1" Address = "0540">
                 <RegisterBit Name ="dummy0540_7_0" StartBit = "7" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      dummy register
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "dummy2" Address = "0541">
                 <RegisterBit Name ="dummy0541_7_0" StartBit = "7" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      dummy register
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "emcu_debug" Address = "0542">
                 <RegisterBit Name ="top_sel" StartBit = "6" BitCount = "2" RW = "2" default = "0">
                     <![CDATA[ 
                      Top debug mode mux for mcu/spi_dma/sm/reg_decoder
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="sel" StartBit = "3" BitCount = "3" RW = "2" default = "0">
                     <![CDATA[ 
                      debug select
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "reg_debug" Address = "0543">
                 <RegisterBit Name ="sel" StartBit = "2" BitCount = "2" RW = "2" default = "0">
                     <![CDATA[ 
                      debug select
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "spi_debug" Address = "0544">
                 <RegisterBit Name ="sel" StartBit = "2" BitCount = "2" RW = "2" default = "0">
                     <![CDATA[ 
                      debug select
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "bist2_sm" Address = "0551">
                 <RegisterBit Name ="fail1" StartBit = "4" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Bist result.
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="fail0" StartBit = "3" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Bist result.
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="done" StartBit = "2" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Bist done
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="mode_start" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Bist mode and start
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn" StartBit = "0" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Bist rstn
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "bisr_en_dmem" Address = "0552">
                 <RegisterBit Name ="pwr_rstn" StartBit = "3" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Bist result.
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="hold_remap" StartBit = "2" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Hold repair status, for gating pwr_rstn
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="soft_rstn" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Soft rst ,used for 1st rst
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="soft_run" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Run second BISR for I_BUFF
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "bisr_st_dmem" Address = "0553">
                 <RegisterBit Name ="so_0" StartBit = "5" BitCount = "2" RW = "0" default = "0">
                     <![CDATA[ 
                      so_0[2:0] : Bisr pararell data of first round BISR
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="fail" StartBit = "2" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Bisr fail information
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="repaired" StartBit = "1" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Bisr repaired information
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="done" StartBit = "0" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      1: done   0:undergoing
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "bist_isram" Address = "0554">
                 <RegisterBit Name ="fail" StartBit = "3" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Bist result.
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="done" StartBit = "2" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Bist done
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="mode_start" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Bist mode and start
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn" StartBit = "0" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Bist rstn
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "bist_rom" Address = "0555">
                 <RegisterBit Name ="done" StartBit = "2" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Bist done
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="mode_start" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Bist mode and start
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="rstn" StartBit = "0" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      Bist rstn
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "bist_rom_st1" Address = "0556">
                 <RegisterBit Name ="crc" StartBit = "7" BitCount = "7" RW = "0" default = "0">
                     <![CDATA[ 
                      CRC LSB[7:0]
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "bist_rom_st2" Address = "0557">
                 <RegisterBit Name ="crc" StartBit = "7" BitCount = "7" RW = "0" default = "0">
                     <![CDATA[ 
                      CRC MSB[7:0]
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "mcu_clock_control" Address = "FFEE">
                 <RegisterBit Name ="isp_mode" StartBit = "7" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="mcu_peri_non_stop" StartBit = "6" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      1: keep mcu peripheral running while mcu stopped by spi flash access
                       0: peripheral will be stopped with mcu*.
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="mcu_clk_div" StartBit = "5" BitCount = "3" RW = "2" default = "1">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="sof_rst" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      EMCI Software Reset (High Active)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="sca_hrst" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "ram_test" Address = "FFEF">
                 <RegisterBit Name ="mcu_tstclk_sel" StartBit = "7" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      1: MCU clock is from external pin0: MCU clock is from crystal/PLL divided by DIV (0xFFED[1])
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="test_mode" StartBit = "4" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      When test_mode of scalar is enabled for embedded mcu output, the bus is decided by following settins.
                       
                       0: 10¡¦b0, adc8_out[7:0], adc8_out_valid, adc8_ckini, flash_mcu_gated, bist_clk, xram_clk, 1¡¦b0, adc_div8_clk , eclk_ng , eclk_n , eclk , shift_in_clk, fclk
                       
                       1: 6¡¦b0, cec_z0_ok , cec_tst[5:0], 17¡¦b1_1111_1111_1111_1111
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ext_ram_bist" StartBit = "3" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Start BIST function for MCU external RAM (512 bytes)
                       0: finished and clear
                       1: start
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="ext_ram_sta" StartBit = "2" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Test result about MCU external RAM
                       0: fail
                       1: ok
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="int_ram_bist" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Start BIST function for MCU internal RAM (256 bytes)
                       0: finished and clear
                       1: start
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="int_ram_sta" StartBit = "0" BitCount = "0" RW = "0" default = "0">
                     <![CDATA[ 
                      Test result about  MCU internal RAM
                       0: fail
                       1: ok
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "xdata_spi_flash_write_protect" Address = "FFF0">
                 <RegisterBit Name ="xdata_flash_en" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      0: Enable xData write to Flash Function (Default)
                       1: Disable xData write to Flash Function 
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "bank_swich_control" Address = "FFFC">
                 <RegisterBit Name ="scalar_addr_remapping" StartBit = "4" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="global_xfr" StartBit = "3" BitCount = "0" RW = "2" default = "1">
                     <![CDATA[ 
                      1: XFR will occupy the address space of all XDATA banks.
                       0: only 0xFFFF will occupy the address of all XDATA banks.
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="global_xram" StartBit = "2" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      Reserved
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="sw_mode" StartBit = "1" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      0: using P3.5 as A16
                       1: using Pbank_switch (0xFFFF)
                     ]]>
                 </RegisterBit>
                 <RegisterBit Name ="bank_en" StartBit = "0" BitCount = "0" RW = "2" default = "0">
                     <![CDATA[ 
                      1: Enable Bank Switching Function for program address space
                       0: Disable Bank Switching, program memory space is 64K byte and GLOBAL_XFR, XDATA_BSTART, XDATA_BSEL still can be used to control XDATA memory space. 
                     ]]>
                 </RegisterBit>
             </Register>
			 
             <Register Name = "XDATA_bank_start" Address = "FFFD">
                 <RegisterBit Name ="XDATA_BSTART" StartBit = "7" BitCount = "7" RW = "2" default = "ff">
                     <![CDATA[ 
                      The start bank number for XDATA access.
                     ]]>
                 </RegisterBit>
             </Register>

             <Register Name = "XDATA_bank_sel" Address = "FFFE">
                 <RegisterBit Name ="XDATA_BSEL" StartBit = "7" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      First bank number for XDATA access.
                     ]]>
                 </RegisterBit>
             </Register>
             <Register Name = "Pbank_switch" Address = "FFFF">
                 <RegisterBit Name ="PBANK_SEL" StartBit = "7" BitCount = "7" RW = "2" default = "0">
                     <![CDATA[ 
                      Bank number for program code access.
                     ]]>
                 </RegisterBit>
             </Register>
		 
         </RegisterSet>
     </RegisterGroup>
  </Group>
</RegisterBase>

